Copper is preferred in forming metal interconnects in ultra-large scale integrated ULSI semiconductor devices. This is because, as semiconductor device geometries continue to scale down below 0.25 μm, and approach 0.13 μm feature sizes, the metal interconnect lines which carry current between devices on a chip begin to dominate the overall circuit speed. In order to enhance interconnect speed and reliability, the semiconductor industry is moving away from blanket deposition and etch of aluminum (Al) based metallization towards single-damascene and dual-damascene interconnect structures with copper (Cu) based metallizations.
Copper is a lower resistivity metal than aluminum, which results in lower RC interconnect delay. Copper has also been shown to have superior electromigration characteristics over aluminum, but is more difficult to process, primarily because it is more difficult to etch, and it acts as a deep level trap in silicon (Si) based devices. The preferred way to process copper interconnects is to etch a line trench, via hole, or a contact hole into a dielectric material, deposit the interconnect metallization to fill the trench or hole, and then polish the metal back to remove any metal from the surface of the substrate or wafer. The resulting metal-filled trenches and holes form the electrical interconnect. Forming an interconnect structure by filling a trench or hole with metal is known as a damascene process. If a trench an underlying via hole are filled simultaneously, it is known as a dual-damascene process.
The process of forming conventional single or dual-damascene structures is shown in FIGS. 1a-1c. In one approach, two insulator layers 120 and 130 are formed on a substrate 100 with an intervening etch-stop layer 125. Substrate 100 is provided with metal layer 110 and a barrier layer 115. Using conventional photolithographic methods and photoresist, the upper and lower insulator layers 120, 130 are etched using a known dual-damascene technique in which successive photoresist patterning is used to create corresponding hole patterns in the layers. After the completion of the thusly formed dual damascene structure, both the via opening 170 and trench opening 150 are filled with metal 180, and any excess material on the surface of the substrate is removed by chemical mechanical polishing (CMP) to produce the structure shown in FIG. 1a. The process can be repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed therebetween that are common in modern semiconductor devices.
Although copper has desirable functional properties that make its use advantageous for forming interconnect and via structures, some reliability issues remain. For example, copper interconnects can suffer from the problem of hillock formation due to stresses resulting from the various high temperature process steps required to form semiconductor devices. Hillocks are spike-like projections that can erupt in response to compressive stresses generated in metal films due to differences in thermal expansion coefficients between adjacent materials in the semiconductor structure. These compressive stresses can cause hillocks to form and consequently protrude from the copper surface, as shown in FIG. 1c. If the hillocks are sufficiently large, they can protrude through any overlying dielectric or other layers and cause short circuiting between metal layers.
It is believed that two major factors affect the formation of hillocks: (1) non-uniform Cu oxide formation on the surface of the copper structure, and (2) high temperatures associated with subsequent chemical vapor deposition (CVD).
Non-uniform Cu native oxide is formed when the Cu film is exposed to the manufacturing atmosphere subsequent to polarization (CMP). Since the oxide formation process is uncontrolled, the oxide layer is typically uneven, and as such it can cause unbalanced expansion of Cu grains when the structure is subjected to high temperatures (e.g. during subsequent CVD). The resulting difference in expansion rates across the uneven copper oxide layer can induces hillocks.
A typical high-temperature process step that can trigger hillock formation is the deposition of an intermetal dielectric (IMD) layer 190 over the structure after the dual damascene interconnect such as 180 in FIG. 1c has been formed. Dielectric layers can be deposited using any of a variety of techniques, such as CVD, and the process is typically carried out at a temperature of at or above 300° Celsius (C). Because of the aforementioned difference in the thermal expansion coefficients, metals such as copper want to expand more than allowed by the substrate, the dielectric, or even oxides on the copper surface. The metal, however, is prevented from doing so, assuming the adhesion between the layers is adequate. As a result, compressive stresses build in the metal film. If these stresses become too large (i.e., where the process temperature exceeds 300° C.), the stresses are relieved by the growth of hillocks at the film surface, as referenced by numeral 200 in FIGS. 1b and 1c. 
To ameliorate the formation of hillocks during the CVD process, current techniques utilize a high temperature annealing step just prior to CVD of the insulating layer. Thus, after the via and trench openings 150, 170 are filled with metal, and CMP has been performed to remove excess Cu material from the top of the semiconductor structure, an annealing step is carried out at a temperature of about 400° C. and is held for about 20 seconds. This annealing step is intended to relax the internal grain structure of the Cu, and to release internal stresses in the Cu generated during Cu plating and the CMP processes.
As noted, these protruding hillocks can adversely affect the ability of overlying dielectric layers to adequately passivate the top surface of the underlying copper structure. If hillocks are large enough, they can protrude through the dielectric layer and result in short-circuit types of defects either immediately or over time, which irrevocably damage the integrated circuit. Thus, it would be advantageous to provide a method for reducing or eliminating such hillocks.